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TMS320C5515
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
www.ti.com
5.12.2
I2C Electrical Data/Timing
Table 5-27. Timing Requirements for I2C Timings (1) (see Figure 5-27 )
CV DD = 1.05 V
CV DD = 1.3 V
NO.
STANDARD
MODE
FAST MODE
UNIT
MIN
MAX
MIN
MAX
1
2
3
4
5
6
t c(SCL)
t su(SCLH-SDAL)
t h(SCLL-SDAL)
t w(SCLL)
t w(SCLH)
t su(SDAV-SCLH)
Cycle time, SCL
Setup time, SCL high before SDA low (for a repeated START
condition)
Hold time, SCL low after SDA low (for a START and a
repeated START condition)
Pulse duration, SCL low
Pulse duration, SCL high
Setup time, SDA valid before SCL high
10
4.7
4
4.7
4
250
2.5
0.6
0.6
1.3
0.6
100 (2)
μs
μs
μs
μs
μs
ns
7
8
t h(SDA-SCLL)
t w(SDAH)
Hold time, SDA valid after SCL low
Pulse duration, SDA high between STOP and START
conditions
0 (3)
4.7
0 (3)
1.3
0.9 (4)
μs
μs
9
t r(SDA)
Rise time, SDA
(5)
1000 20 + 0.1C b
(6)
300
ns
10
t r(SCL)
Rise time, SCL (5)
1000 20 + 0.1C b (6)
300
ns
11
t f(SDA)
Fall time, SDA
(5)
300 20 + 0.1C b
(6)
300
ns
12
t f(SCL)
Fall time, SCL (5)
300 20 + 0.1C b (6)
300
ns
13
t su(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition)
4
0.6
μs
14
15
t w(SP)
C b (6)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
400
0
50
400
ns
pF
(1)
(2)
(3)
(4)
(5)
(6)
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down. Also these pins are not 3.6 V-tolerant (their V IH cannot go above DV DDIO + 0.3 V).
A Fast-mode I 2 C-bus? device can be used in a Standard-mode I 2 C-bus system, but the requirement t su(SDA-SCLH) ≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line t r max + t su(SDA-SCLH) = 1000 + 250 = 1250 ns
(according to the Standard-mode I 2 C-Bus Specification) before the SCL line is released.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V IHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
The maximum t h(SDA-SCLL) has only to be met if the device does not stretch the low period [t w(SCLL) ] of the SCL signal.
The rise/fall times are measured at 30% and 70% of DV DDIO . The fall time is only slightly influenced by the external bus load (C b ) and
external pullup resistor. However, the rise time (t r ) is mainly determined by the bus load capacitance and the value of the pullup resistor.
The pullup resistor must be selected to meet the I2C rise and fall time values specified.
C b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
SDA
11
9
8
6
14
10
4
5
13
SCL
Stop
Start
3
1
7
12
Repeated
3
2
Stop
Start
Figure 5-27. I2C Receive Timings
114
Peripheral Information and Electrical Specifications
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